The present invention relates to field effect transistor (FET) devices, and more specifically, to contacts for FET devices.
Field effect transistor devices include a gate stack arranged over a channel region and source and drain active regions adjacent to the gate stack. The source and drain regions are often covered with conductive contacts that include metallic or silicide material.
FinFET devices are multi-gate FET devices that include a semiconductor fin arranged on a substrate. The fin provides a channel region with three surfaces with a gate stack patterned on the channel region. Active source and drain regions are arranged on the fin adjacent to the gate stack. FinFET devices improve FET performance while reducing the size of the FET devices.
Previous finFET fabrication processes included patterning a fin from a semiconductor material using a lithographic patterning and etching process such as reactive ion etching. Often a dummy gate stack is patterned on the fins to define a channel region on the fin. Subsequently, active regions are formed on the fin by implanting dopants or epitaxially growing semiconductor material on exposed portions of the fin. Following the formation of the active regions, the dummy gate stack may be removed and replaced with a gate stack that is formed over the channel region of the fins.
Often an insulator such as an oxide material is grown over the active regions. The insulator is patterned and etched using a photolithographic etching process that removes portions of the insulator material to expose the active regions of the FET devices. A conductive material is deposited on the active regions and a planarization process is performed to remove overburdened conductive material. Properly aligning the photolithographic mask used in removing the insulator material can be problematic, thus it is desirable to form FET devices with a process with a minimal number of photolithographic masks.